1. Field of the Invention
The present invention relates to a display device, more particularly to an apparatus and method for data transmission, and an apparatus and method for driving an image display device using the same.
2. Discussion of the Related Art
Recently, various flat panel displays have been developed that are lighter and less bulky than cathode ray tubes. Examples of such flat panel displays include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and a light emitting display (LED). An LCD displays an image by controlling the light transmittance of liquid crystal cells in accordance with a video signal. In an active matrix type LCD, a switching element is provided in each liquid crystal cell. The active matrix type LCD typically includes a thin film transistor (TFT) as the switching element.
FIG. 1 shows a schematic diagram of an apparatus for driving an LCD according to the related art. Referring to FIG. 1, the related art apparatus for driving an LCD includes an image display unit 2 including liquid crystal cells formed in each pixel region defined by crossings of first to n-th gate lines GL1 to GLn with first to m-th data lines DL1 to DLm, a data driver 4 supplying analog video signals to the data lines DL1 to DLm, a gate driver 6 supplying scan pulses to the gate lines GL1 to GLn, and a timing controller 8 aligning externally provided input Data to supply the aligned data to the data driver 4, generating data control signals DCS to control the data driver 4, and generating gate control signals GCS to control the gate driver 6.
The image display unit 2 includes a transistor array substrate (not shown), a color filter array substrate (not shown), a spacer (not shown), and a liquid crystal (not shown). The transistor array substrate and the color filter array substrate face and are bonded to each other. The spacer maintains a uniform cell gap between the two substrates. The liquid crystal is filled in the cell gap area maintained by the spacer.
The image display unit 2 includes TFTs formed in the pixel regions defined by crossings of the gate lines GL1 to GLn and the data lines DL1 to DLm. The TFTs are electrically connected to the liquid crystal cells. The TFTs supply analog video signals from the data lines DL1 to DLm to the liquid crystal cells in response to the scan pulses from the gate lines GL1 to GLn.
A liquid crystal cell includes common electrodes and pixel electrodes connected to the thin film transistor and facing each other, and a liquid crystal interposed between the common electrodes and the pixel electrodes. Thus, the liquid crystal cell is equivalent to a liquid crystal capacitor Clc. The liquid crystal cell also includes a storage capacitor Cst connected to a previous gate line to maintain the analog video signals filled in the liquid crystal capacitor Clc until the next analog video signal is charged in the liquid crystal capacitor Clc.
The timing controller 8 aligns the externally provided Data input data in a format suitable for properly driving of the image display unit 2. The timing controller 8 supplies the aligned RGB data to the data driver 4. Also, the timing controller 8 generates the data control signals DCS and the gate control signals GCS using a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync, which are externally provided to control a driving timing of the data driver 4 and the gate driver 6.
The gate driver 6 includes a shift register (not shown) that sequentially generates scan pulses, for example, gate high pulses in response to a gate start pulse and a gate shift clock generated as gate control signals GCS from the timing controller 8. The gate driver 6 sequentially supplies the gate high pulses to the gate lines GL of the image display unit 2 to turn on the TFT connected to the gate lines GL.
The data driver 4 converts the aligned RGB data from the timing controller 8 into analog video signals in response to the data control signals DCS supplied from the timing controller 8. During each horizontal period, the data driver 4 supplies to the data lines DL1 to DLm the analog video signals corresponding to one horizontal line when the scan pulses are supplied into the gate lines GL1 to GLn. For example, the data driver 4 selects a gamma voltage having a predetermined level depending on a gray level value of the aligned RGB data and supplies the selected gamma voltage to the data lines DL1 to DLm. Then, the data driver 4 inverts a polarity of the analog video signals supplied to the data lines DL in response to a polarity control signal.
FIG. 2 is a schematic diagram illustrating a data transmission bus between a timing controller and a data driver in the related art apparatus of FIG. 1. The timing controller 8 includes a control signal generator 22 generating the control signals DCS and GCS, and a data aligner 24 aligning the source Data and supplying the Data aligned data to the data driver 4. The control signal generator 22 generates the gate control signals GCS (GSC, GSP and GOE) and the data control signals DCS (SSC, SSP, SOE and POL) using the main clock MCLK, the data enable signal DE, and the horizontal and vertical synchronizing signals Hsync and Vsync, which are externally provided. The gate control signals GCS are supplied to the gate driver 6 through respective transmission lines included in a gate control signal bus (not shown). The data control signals DCS are supplied to the data driver 4 through respective transmission lines included in a data control signal bus 12.
The data aligner 24 aligns the externally provided input source Data in a manner suitable for a bus transmission and synchronizes the aligned RGB data with a source shift clock SSC signal to supply the synchronized data to the data driver 4. For example, the data aligner 24 supplies the aligned RGB data to the data driver 4 through red, green and blue data buses 14, 16, and 18 as shown in Table 1. If each of the aligned RGB data is a 6-bit data, each of the data buses 14, 16 and 18 includes six data transmission lines to transfer the 6-bit data. Thus, the number of the data transmission lines becomes 18.
TABLE 1BitGrey levelD5D4D3D2D1D00000000100000120000103000011.....................63 111111
In Table 1, D0˜D5 represent one of R, G, and B data values.
The timing controller 8 supplies data corresponding to one pixel (for example, 18 bits of respective 6 bits of R, G, and B) to the data driver 4 using eighteen data transmission lines from the three data buses 14, 16, and 18. However, if the data corresponding to one pixel are supplied from the timing controller 8 to the data driver 4, electromagnetic interference seriously occurs due to transition of the data. For example, if the current pixel data have a bit value of “0” and the next pixel data have a bit value of “1”, a transition occurs in all the bits and causes high electromagnetic interference. Particularly, if resolution and size of the image display unit increase, electromagnetic interference is more severe.